Hardware/Software Co-Design

Ralf Dreesen, Michael Thies, Uwe Kastens: Type Analysis on Bitstring Expressions. In Proceedings of the 9th Workshop on Optimizations for DSP and Embedded Systems (ODES-9). April 2011
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Ralf Dreesen, Thorsten Jungeblut, Michael Thies, Uwe Kastens: Dependence Analysis of VLIW Code for Non-Interlocked Pipelines. In Proceedings of the 8th Workshop on Optimizations for DSP and Embedded Systems (ODES-8). 2010
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Stephanie Drzevitzky, Uwe Kastens, Marco Platzner: Proof-Carrying Hardware: Concepts and Prototype Tool Flow for Online Verification. In International Journal of Reconfigurable Computing, vol. 2010, pp. 11. 2010 . Article ID 180242.
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Ralf Dreesen, Thorsten Jungeblut, Michael Thies, Mario Porrmann, Uwe Kastens, Ulrich Rückert: A Synchronization Method for Register Traces of Pipelined Processors. In Analysis, Architectures and Modelling of Embedded Systems, IFIP Advances in Information and Communication Technology, vol. 310, pp. 207-217. Springer Boston, 2009
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Stephanie Drzevitzky, Uwe Kastens, Marco Platzner: Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (Los Alamitos, CA, USA), pp. 189-194. IEEE Computer Society, December 2009
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Ralf Dreesen, Michael Hußmann, Michael Thies, Uwe Kastens: Register Allocation for Processors with Dynamically Reconfigurable Register Banks. In Proceedings of the 5rd Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 5rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2007). 2007
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Christian Sauer, M. Gries, Jörg-Christian Niemann, Mario Porrmann, Michael Thies: Application-driven Development of Concurrent Packet Processing Platforms. In PARELEC 2006, International Conference on Parallel Computing in Electrical Engineering, Bialystok, Poland. 2006
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Peter Bleckmann, Gunnar Schomaker, Adrian Slowik: Virtualization with Prefetching Abilities based on iSCSI. In Proceedings of the International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI 2004) (Nice, France). 2004
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Gunnar Hagen, Jörg-Christian Niemann, Mario Porrmann, Christian Sauer, Adrian Slowik, Michael Thies: Developing an IP-DSLAM Benchmark for Network Processor Units. In ANCHOR 2004, Advanced Networking and Communications Hardware Workshop, held in conjunction with the 31st Annual International Symposium on Computer Architecture (ISCA 2004), Munich - Germany. 19~-~23~ # jun 2004
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Matthias Grünewald, Uwe Kastens, Dinh Khoi Le, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert, Michael Thies, Adrian Slowik: Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. In PARELEC 2004, International Conference on Parallel Computing in Electrical Engineering, Dresden, Germany. 2004
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Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies: Feedback Driven Instruction-Set Extension. In Proceedings of ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04) (Washington, D.C., USA). 2004
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D. Fischer, J. Teich, R. Weper, Michael Thies: BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. In Journal of Circuits, Systems, and Computers, vol. 12, no. 3, pp. 353-375. 2003
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O. Bornorden, N. Brühls, Uwe Kastens, Dinh Khoi Le, Friedhelm Meyer auf der Heide, Mario Porrmann, Ulrich Rückert, Adrian Slowik, Michael Thies: A holistic methodology for network processor design. In Proceedings of Workshop on High-Speed Local Networks (HSLN) at Local Computer Networks (LCN2003) (Bonn, Germany). 2003
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D. Fischer, J. Teich, Michael Thies, R. Weper: Efficient Architecture/Compiler Co-Exploration for ASIPs. In Proceedings of ACM SIG International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2002) (Grenoble, France 2002). 2002
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D. Fischer, Uwe Kastens, J. Teich, Michael Thies, R. Weper: Design Space Characterization for Architecture/Compiler Co-Exploration. In Proceedings of ACM SIG International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2001) (Georgia, Atlanta, USA), pp. 108-115. 2001
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Peter Pfahler, C. Nagel, Franz-Josef Rammig, Uwe Kastens: Design of a VLIW Architecture Constructed from Standard RISC Chips: A Case Study of Hardware/Software Software Codesign. In Proceedings of Euromicro 1993, Microprocessing and Microprogramming (Amsterdam). Nordholland, 1993
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Christian Ewering: A New Allocation Method for the Synthesis of Partitioned Busses. In GME/GI/ITG-Fachtagung. 1990
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Christian Ewering, Gunter Gerhardt: PASS: High Level Synthesis. In Proceedings of Euromicro 1990, Microprocessing and Microprogramming. 1990
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Christian Ewering: Automatic High-Level Synthesis of Partitioned Busses. In IEEE Int. Conf. on Computer Aided Design, pp. 304-307. 1990
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Christian Ewering: Automatic high level synthesis of partitioned busses. Tech. Rep., no. tr-ri-90-66. 1990
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Gerhard Goos, Uwe Kastens: Programming Languages and the Design of Modular Programs. In Peter Hibbard and Stephen Schuman (eds.): Constructing Quality Software (Amsterdam), pp. 153-186. North-Holland, 1977
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