Dr. Ralf Dreesen

Address:
Ralf Dreesen
University of Paderborn
Faculty of Computer Science, Electrical Engineering and Mathematics
Fürstenallee 11
33102 Paderborn
Germany

Room: F2.301
Tel.: +49 5251 60-
Fax: +49 5251 60-

Publications

  • Ralf Dreesen. Generating Interlocked Instruction Pipelines from Specifications of Instruction Sets. In Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2012.(to appear)
  • Ralf Dreesen.ViDL: A Versatile ISA Description Language. In 19th Annual IEEE International Conference and Workshops on the Engineering of Computer Based Systems (ECBS-19), April 2012.
  • Ralf Dreesen. Generating Processors from Specifications of Instruction Sets. Dissertation, University of Paderborn, Germany, 2011.
  • Ralf Dreesen, Michael Thies, Uwe Kastens. Type Analysis on Bitstring Expressions. Proceedings of the 9th Workshop on Optimizations for DSP and Embedded Systems (ODES-9), April 2011 (download)
  • Thorsten Jungeblut, Ralf Dreesen, Mario Porrmann, Michael Thies, Ulrich Rückert and Uwe Kastens. A Framework for the Design Space Exploration of Software-Defined Radio Applications. In 2nd International ICST Conference on Mobile Lightweight Wireless Systems, 2010.
  • Ralf Dreesen, Thorsten Jungeblut, Michael Thies, Uwe Kastens. Dependence Analysis of VLIW Code for Non-Interlocked Pipelines. Proceedings of the 8th Workshop on Optimizations for DSP and Embedded Systems (ODES-8), April 2010 (download)
  • Thorsten Jungeblut, Christoph Puttmann, Ralf Dreesen, Mario Porrmann, Michael Thies, Ulrich Rückert, Uwe Kastens: Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography.  Advances in Radio Science 2010
  • Ralf Dreesen, Thorsten Jungeblut, Michael Thies, Mario Porrmann, Uwe Kastens, Ulrich Rückert. A Synchronization Method for Register Traces of Pipelined Processors. Analysis, Architectures and Modelling of Embedded Systems, pp. 207-217, Springer (ISBN 978-3-642-04283-6), September 2009.
  • Thorsten Jungeblut, Ralf Dreesen, Mario Porrmann, Ulrich Rückert and Ulrich Hachmann. Design Space Exploration for Resource Efficient VLIW-Processors. In University Booth of the Design, Automation and Test in Europe (DATE) conference, 2008.
  • Ralf Dreesen, Michael Hußmann, Michael Thies and Uwe Kastens. Register Allocation for Processors with Dynamically Reconfigurable Register Banks. In Proceedings of the 5rd Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with the 5rd IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2007), March 2007. (download)
  • Ralf Dreesen. Registerzuteilung für Prozessor-Cluster mit dynamisch rekonfigurierbaren Registerbänken. Diplomarbeit, Universität Paderborn, 2006. (download)

Compiler-Tools

As a member of the MxMobile project, I've developed compiler-tools for the CoreVA mobile processor. The toolchain consists of an optimizing C-compiler, an instruction set simulator, an assembler, a disassembler and a linker.

The compiler features CoreVA-specific modules and optimizations, such as a parallelizing VLIW scheduler, which considers restrictions slots, fills branch-delay-slots and avoids data-hazards. Besides, the compiler supports SIMD instructions and conditional execution.

Substantial parts of the compiler are generated from an instruction set specification (formulated in UPSLA). To generate the other tools as well, I have developed respective generators for the assembler, disassembler and linker. These generators have then been applied for the CoreVA instruction set.

In addition, an instruction set specific optimization has been developed for the assembler, which aligns branch targets. The optimization reduces control hazards and increases the instruction throughput as a result. The CoreVA toolchain supports debugging information and relocation of code.

Generating Processors and Simulators

In my PhD thesis, I've developed a system to accelerate and simplify the engineering of application specific processors. The system consists of several generators and the instruction set specification language ViDL. In contrast to alternative approaches, ViDL strictly abstracts from all microarchitectural aspects of processors. This property increases readability as well as reliability and allows for generation of diverse Implementations. Generators have been developed, which produce fast instruction set simulators (C), web-based simulators (HTML/JavaScript) and processors (VHDL).

The processor generator yields several implementations of different pipeline structure. The structure is derived from a user-defined target frequency, instruction semantics and information on propagation delays of the targeted chip technology. Generators are entirely automated, i.e. a user does not have to supply any aspect of the microarchitecture. Data-hazards are automatically resolved using forwarding and interlocking. Control-hazards are resolved using branch prediction and speculative execution. Resource hazards are avoided by a conflict free allocation of resources. These error-prone tasks are thereby shifted from the user to the generator.

To show, that the system can successfully be applied in practice, realistic instruction sets have been specified and generated implementations have been evaluated. The following instruction sets have been specified: ARM, MIPS, Power, CoreVA and SRC.

Further information and generated web-simulators can be found on www.vidl.de.

Teaching (Tutorials)

WS 10/11 Modellierung
SS 10 Funktionale Programmierung
WS 09/10 Modellierung
SS 09 Datenstrukturen und Algorithmen
WS 08/09 Funktionale Programmierung
WS 07/08 Modellierung
SS 07 Grundlagen der Programmierung

Organization

I'm managing the boxes on floor D3, where students can drop their solutions to execises. Information on how to "order" one of these boxes is supplied on request (university staff only).

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